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ICM7243
August 1997
8-Character, MicroprocessorCompatible, LED Display Decoder Driver
Description
The ICM7243 is an 8-character, alphanumeric display driver and controller which provides all the circuitry required to interface a microprocessor or digital system to a 14-segment or 16-segment display. It is primarily intended for use in microprocessor systems, where it minimizes hardware and software overhead. Incorporated on-chip are a 64-character ASClI decoder, 8 x 6 memory, high power character and segment drivers, and the multiplex scan circuitry. 6-bit ASCll data to be displayed is written into the memory directly from the microprocessor data bus. Data location depends upon the selection of either Sequential (MODE = 1) or Random access mode (MODE = 0). In the Sequential Access mode the first entry is stored in the lowest location and displayed in the "left-most" character position. Each subsequent entry is automatically stored in the next higher location and displayed to the immediate "right" of the previous entry. A DISPlay FULL signal is provided after 8 entries; this signal can be used for cascading devices together. A CLeaR pin is provided to clear the memory and reset the location counter. The Random Access mode allows the processor to select the memory address and display digit for each input word. The character multiplex scan runs whenever data is not being entered. It scans the memory and CHARacter drivers, and ensures that the decoding from memory to display is done in the proper sequence. Intercharacter blanking is provided to avoid display ghosting.
Features
* 14-Segment and 16-Segment Fonts with Decimal Point * Mask Programmable for Other Font-Sets Up to 64 Characters * Microprocessor Compatible * Directly Drives LED Common Cathode Displays * Cascadable Without Additional Hardware * Standby Feature Turns Display Off; Puts Chip in Low Power Mode * Sequential Entry or Random Entry of Data Into Display * Single +5V Operation * Character and Segment Drivers, All MUX Scan Circuitry, 8 x 6 Static Memory and 64-Character ASCll Font Generator Included On-Chip
Ordering Information
PART NUMBER ICM7243AIJL ICM7243AIPL ICM7243BIJL ICM7243BlPL TEMP. RANGE (oC) -25oC to 85 -25oC to 85 -25oC to 85 -25 to 85 PACKAGE 40 Ld CERPDIP 40 Ld PDIP 40 Ld CERPDIP 40 Ld PDIP PKG. NO. F40.6 E40.6 F40.6 E40.6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
3162.1
9-21
ICM7243 Pinouts
ICM7243A (16-SEGMENT CHARACTER) (PDIP, CERDIP) TOP VIEW
VDD SEG m SEG e SEG g1 SEG k SEG c SEG d1 SEG a1 SEG a2 D0 D1 D2 D3 D4 D5 CS WR CHAR 8 CHAR 7 CHAR 6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 SEG l 39 SEG g2 38 SEG b 37 SEG i 36 SEG f 35 SEG d2 34 DP 33 SEG h 32 SEG j 31 MODE 30 A0/SEN 29 A1/CLR 28 A2/DISP FULL 27 OSC/OFF 26 CHAR 1 25 CHAR 2 24 CHAR 3 23 CHAR 4 22 VSS 21 CHAR 5
ICM7243B (14-SEGMENT CHARACTER) (PDIP, CERDIP) TOP VIEW
VDD SEG e SEG g1 SEG k SEG c SEG d SEG a D0 D1 D2 D3 D4 D5 CS CS CS WR CHAR 8 CHAR 7 CHAR 6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 SEG m 39 SEG l 38 SEG g2 37 SEG b 36 SEG i 35 SEG f 34 DP 33 SEG h 32 SEG j 31 MODE 30 A0/SEN 29 A1/CLR 28 A2/DISP FULL 27 OSC/OFF 26 CHAR 1 25 CHAR 2 24 CHAR 3 23 CHAR 4 22 VSS 21 CHAR 5
9-22
ICM7243 Functional Block Diagram
Q DATA INPUT D0 - D5 DATA D LATCHES CL 8x6 6 DATA D0 MEMORY CLR ADR CL D1 17 64 x 17 ROM
(NOTE 1)
(NOTE 1)
SEGMENT DRIVERS
SEGMENT OUTPUTS SEG x
WR (NOTE 1) CS CS CS
ONE SHOT
8
CL MODE D
8
8 CHARACTER CHARACTER DRIVERS
CHAR N CHARACTER OUTPUTS
SEL A0/SEN
3 CL D ADDRESS LATCHES
SEL
A1/CLR
MUX
CL D Q CONTROL LATCH
CL EN SEQUENTIAL SEQUENTIAL ADDRESS 3 COUNTER CLR OVERFLOW 3
ADDRESS MULITPLEXER MULTIPLEXER AND DECODER
A2/DISP FULL
OSC/OFF
OSCILLATOR MULTIPLEX OSCILLATOR
CHARACTER MULTIPLEX COUNTER
INTER-CHARACTER BLANKING
NOTE: 1. ICM7243A has only one CS and no CS. ICM7243B has 15 Segments.
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ICM7243
Absolute Maximum Ratings
Supply Voltage VDD - VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V Input Voltage (Any Terminal) . . . . . . . . . . . VDD +0.3V to VSS -0.3V CHARacter Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . 300mA SEGment Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 55 N/A CERDIP Package . . . . . . . . . . . . . . . . 50 10 Maximum Junction Temperature CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER DC CHARACTERISTICS
VDD = 5V, VSS = 0V, TA = 25oC, Unless Otherwise Specified TEST CONDITIONS MIN TYP MAX UNITS
Supply Voltage (VDD - VSS), VSUPP Operating Supply Current, IDD Quiescent Supply Current, ISTBY Input High Voltage, VIH Input Low Voltage, VIL Input Current, IIN CHARacter Drive Current, ICHAR CHARacter Leakage Current, ICHLK SEGment Drive Current, ISEG SEGment Leakage Current, ISLK DISPlay FULL Output Low, VOL DISPlay FULL Output High, VOH Display Scan Rate, fDS IOL = 1.6mA lIH = 100A VSUPP = 5V, VOUT = 2.5V VSUPP = 5V, VOUT = 1V VSUPP = 5.25V, 10 Segments ON, All 8 Characters VSUPP = 5.25V, OSC/OFF Pin < 0.5V, CS = VSS
4.75 2 -10 140 14 2.4 -
5.0 180 30 190 19 0.01 400
5.25 250 0.8 +10 100 10 0.4 -
V mA A V V A mA A mA A V V Hz
Electrical Specifications
Drive levels 0.4V and 2.4V, timing measured at 0.8V and 2.0V. VDD = 5V, TA = 25oC, Unless Otherwise Specified TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER AC CHARACTERISTICS WR, CLeaR Pulse Width Low, tWPI WR, CLeaR Pulse Width High (Note 1), tWPH Data Hold Time, tDH Data Setup Time, tDS Address Hold Time, tAH Address Setup Time, tAS CS, CS Setup Time, tCS Pulse Transition Time, tT SEN Setup Time, tSEN Display Full Delay, tWDF
300 0 250 125 40 0 0 700
250 250 -100 150 15 -25 480
100 -
ns ns ns ns ns ns ns ns ns ns
Capacitance
PARAMETER Input Capacitance, ClN Output Capacitance, CO TEST CONDITIONS (Note 2) (Note 2) MIN TYP 5 5 MAX UNITS pF pF
NOTES: 1. In Sequential mode WR high must be TSEN +TWDF . 2. For design reference only, not tested.
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ICM7243 Timing Waveforms
CS tCS CS tAH tAS ADDRESS VALID tWPI WRITE tDS tT DATA VALID tT tDH tWC tWHP
FIGURE 1. RANDOM ACCESS TIMING
CHAR 1 tSEN CLEAR CHAR 2 CHAR 8
WR
tWPH
SEN tWDF DISPLAY FULL
FIGURE 2. SEQUENTIAL ACCESS MODE TIMING (MODE = 1)
~5s
INTERNAL INTER-CHARACTER BLANKING SIGNAL CHAR 1
~300s
CHAR 2
CHAR 3
CHARACTERS DRIVE SIGNALS
CHAR 4
CHAR 5 INTER-CHARACTER BLANKING
CHAR 6
CHAR 7
CHAR 8
FIGURE 3. DISPLAY CHARACTERS MULTIPLEX TIMING DIAGRAM
9-25
ICM7243 Performance Curves
30 500 VDD = 5.5V ICHAR (mA) 400 300 5.0V
VDD = 5.5V 20 ISEG (mA)
5.0V 10 4.5V
200 100 4.5V
0 0 1 2 SEGMENT VOLTAGE (V) 3 0 1 2 SEGMENT VOLTAGE (V) 3
FIGURE 4. SEGMENT CURRENT vs OUTPUT VOLTAGE
FIGURE 5. CHARACTER CURRENT VS OUPUT VOLTAGE
Pin Descriptions
SIGNAL ICM7243A(B) D0 - D5 10 - 15 (8 - 13) 16 (14 - 16) 17 Six-Bit ASCll Data input pins (active high). PIN FUNCTION
CS, CS
Chip Select from P address decoder, etc.
WR
WRite pulse input pin (active low). For an active high write pulse, CS can be used, and WR can be used as CS. Selects data entry MODE. High selects Sequential Access (SA) mode where first entry is displayed in "leftmost" character and subsequent entries appear to the "right". Low selects the Random Access (RA) mode where data is displayed on the character addressed via A0 - A2 Address pins. In RA mode it is the LSB of the character Address. In SA mode it is used for cascading devices for displays of more than 8 characters (active high enables device controller). In RA mode this is the second bit of the address. In SA mode, a low input will CLeaR the Serial Address Counter, the Data Memory and the display. In RA mode this is the MSB of the Address. In SA mode, the output goes high after eight entries, indicating DISPlay FULL. OSCillator input pin. Adding capacitance to VDD will lower the internal oscillator frequency. An external oscillator can be applied to this pin. A low at this input sets the device into a (shutdown) mode, shutting OFF the display and oscillator but retaining data stored in memory. SEGment driver outputs.
MODE
31
A0/SEN
30
A1/CLeaR
29
A2/DISPlay FULL OSC/OFF
28
27
SEG a - SEG m, DP CHARacter 1 - 8
2 - 9, 32 - 40 (2 - 7), (32 - 40) 18 - 21, 23 - 26
CHARacter driver outputs.
9-26
ICM7243 Test Circuit
17 SEGMENTS
CHAR 8 CHAR 7 CHAR 6 CHAR 5 CHAR 4 CHAR 3 CHAR 2 CHAR 1
VDD SEG m SEG e SEG g1 SEG k SEGMENTS SEG c SEG d1 SEG a1 SEG a2 D0 VDD D1 D2 D3 D4 D5 CS WR CHAR 8 CHAR 7 CHAR 6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ICM7243A
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
SEG l SEG g2 SEG b SEG i SEG f SEG d2 DP SEG h SEG j MODE (SA/RA) A0/SEN A1/CLR A2/DISP FULL OSC/OFF CHAR 1 CHAR 2 CHAR 3 CHAR 4 DISPLAY FULL OUTPUT VDD NC (FOR SA MODE) VDD SEGMENTS 8 CHARACTERS
CHAR 5
FIGURE 6.
9-27
ICM7243 Typical Applications
8 CHARACTERS 8 CHARACTERS
+5V CHAR RRI RBR8 RBR7 IM6403 UART CLR CS ICM7243B SEN CS,WR D0 - D5 DISP FULL CS CLR CS SEN CS,WR D0 - D5 CS ICM7243B SEG CHAR SEG
DISP FULL ETC.
RBR1 - RBR6 DRR DR
6 BIT BUS
+5V +5V 20K OUT V+ SEN TR ICL7555 DELAY TH 200pF CS CLR CHAR SEG ICM7243B DISP FULL CS D0 - D5 CS WR
+5V D0 - D5 CS SEN ICM7243B CS CLR CHAR SEG DISP FULL ETC. CS WR
8 CHARACTERS
8 CHARACTERS
FIGURE 7. DRIVING TWO ROWS OF CHARACTERS FROM A SERIAL INPUT
9-28
ICM7243 Typical Applications
(Continued)
8-CHARACTER LED DISPLAY 8-CHARACTER LED DISPLAY
8-CHARACTER LED DISPLAY
8
NOTE
8
NOTE
8
NOTE
CLR
CLR
CHAR SEG
CLR
CHAR SEG
CLR
CHAR SEG
+5V +5V
SEN MODE WR D0 - D5
DISP FULL VDD VSS +5V +5V
CS
SEN MODE WR D0 - D5
DISP FULL VDD VSS +5V +5V
CS
SEN MODE WR D0 - D5
DISP FULL VDD VSS +5V
CS
DATA BUS WR, (CS) CS, (WR)
6
6
6
FIRST 8 CHARACTERS
SECOND 8 CHARACTERS
NTH 8 CHARACTERS
NOTE: 17 for ICM7243A, 15 for ICM7243B. FIGURE 8. MULTICHARACTER DISPLAY USING SEQUENTIAL ACCESS MODE
+5V
+5V
+5V
+5V 1K
+5V 1.4APEAK 2N6034
100 1mA 2N2219 SEG
100
SEG 300 1K ICM7243 25 R ON = 4 CHAR (100mAPEAK) 2N2219
ICM7243
14 (100mAPEAK)
CHAR R ON = 4
14mA 2N6034 1.4APEAK GND GND 1K GND
GND
GND
FIGURE 9A. COMMON CATHODE DISPLAY
FIGURE 9B. COMMON ANODE DISPLAY
FIGURE 9. DRIVING LARGE DISPLAYS
9-29
ICM7243 Typical Applications
(Continued)
8 CHARACTERS 8 CHARACTERS 8 CHARACTERS 8 CHARACTERS
ICM7243A/B CS A2 A1 A0 D0 - D5 WR P22 P21 80C35 80C48 P20
ICM7243A/B CS A2 A1 A0 D0 - D5 WR
ICM7243A/B CS A2 A1 A0 D0 - D5 WR
ICM7243A/B CS A2 A1 A0 D0 - D5 WR
DB7 DB6 DB5 - DB0 WR 6 BIT BUS
FIGURE 10. RANDOM ACCESS 32-CHARACTER DISPLAY IN A 80C48 SYSTEM
Display Font and Segment Assignments
a1 f h g1 e m d2 0 0 l i a2 j g2 k d1 c DP b
0
1
D5, D4
1
0
1
1
D3 D2 D1 D0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
FIGURE 11. ICM7232A 16-SEGMENT CHARACTER FONT WITH DECIMAL POINT
9-30
ICM7243 Display Font and Segment Assignments
a1 f h g1 e m d2 0 0 l d a i (Continued)
a2 j g2 k d1 c DP b
0
1
D5, D4
1
0
1
1
D3 D2 D1 D0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
NOTE: Segments a and d appear as 2 segments each, but both halves are driven together. FIGURE 12. ICM7243B 14-SEGMENT CHARACTER FONT WITH DECIMAL POINT
VDD SEGMENT DRIVER VLED = 1.6V RTYPICAL = 100
R
SEG x
DISPLAY
CHARACTER DRIVER CHAR N RDS(ON) ~ 4 VSS SEGMENT LEDs
FIGURE 13. SEGMENT AND CHARACTER DRIVERS OUTPUT CIRCUIT
9-31
ICM7243 Detailed Description
WR, CS, CS - These pins are immediately functionally ANDed, so all actions described as occurring on an edge of WR, with CS and CS enabled, will occur on the equivalent (last) enabling or (first) disabling edge of any of these inputs. The delays from CS pins are slightly (about 5ns) greater than from WR or CS due to the additional inverter required on the former. MODE - The MODE pin input is latched on the falling edge of WR (or its equivalent, see above). The location (in Data Memory) where incoming data will be placed is determined either from the Address pins or the Sequential Address Counter. This is controlled by MODE input. MODE also controls the function of A0/SEN, A1/CLR, and A2/DlSPlay FULL lines. Random Access Mode - When the internal mode latch is set for Random Access (RA) (MODE latched low), the Address input on A0, A1 and A2 will be latched by the falling edge of WR (or its equivalent). Subsequent changes on the Address lines will not affect device operation. This allows use of a multiplexed 6-bit bus controlling both address and data, with timing controlled by WR. Sequential Access Mode - If the internal latch is set for Sequential Access (SA), (MODE latched high), the Serial ENable input or SEN will be latched on the falling edge of WR (or its equivalent). The CLR input is asynchronous, and will force-clear the Sequential Address Counter to address 000 (CHARacter 1), and set all Data Memory contents to 100000 (blank) at any time. The DISPlay FULL output will be active in SA mode to indicate the overflow status of the Sequential Address Counter. If this output is low, and SEN is (latched) high, the contents of the Counter will be used to establish the Data Memory location for the Data input. The Counter is then incremented on the rising edge of WR. If SEN is low, or DISPlay FULL is high, no action will occur. This allows easy "daisy-chaining" of display drivers for multiple character displays in a Sequential Access mode. Changing Modes - Care must be exercised in any application involving changing from one mode to another. The change will occur only on a falling edge of WR (or its equivalent). When changing mode from Sequential Access to Random Access, note that A2/DlSPlay FULL will be an output until WR has fallen low, and an Address drive here could cause a conflict. When changing from Random Access to Sequential Access, A1/CLR should be high to avoid inadvertent clearing of the Data Memory and Sequential Address Counter. DISPlay FULL will become active immediately after the rising edge of WR. Data Entry - The input Data is latched on the rising edge of WR (or its equivalent) and then stored in the Data Memory location determined as described above. The six Data bits can be multiplexed with the Address information on the same lines semiconductor products are Timing is controlled All Intersil in Random Access mode. manufactured, assembled and tested under ISO9000 quality systems certification. by the WR input. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate OSC/OFF - The no responsibility is assumed by Intersil or its subsidiaries and reliable. However, device includes a relaxation oscillator with for its use; nor for any infringements of patents or other rights of third parties which an result from its use. No license a nominal frequency of 200kHz. may internal capacitor and is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
pin, this frequency can be reduced as far as desired. Alternatively, an external signal can be injected on this pin. The oscillator (or external) frequency is pre-divided by 64, and then further divided by 8 in the Multiplex Counter, to drive the CHARacter drive lines (see Figure 3). An inter-character blanking signal is derived from the pre-divider. An additional comparator on the OSC/OFF input detects a level lower than the relaxation oscillator's range, and blanks the display, disables the DISPlay FULL output (if active), and clears the pre-divider and Multiplex Counter. This puts the circuit in a low-power-dissipation mode in which all outputs are effectively open circuits, except for parasitic diodes to the supply lines. Thus a display connected to the output may be driven by another circuit (including another ICM7243) without driver conflicts. Display Output - The output of the Multiplex Counter is decoded and multiplexed into the address input of the Data Memory, except during WR operations (in Sequential Access mode, with SEN high and DISPlay FULL low), when it scans through the display data. The address decoder also drives the CHARacter outputs, except during the inter-character blanking interval (nominally about 5s). Each CHARacter output lasts nominally about 300s, and is repeated nominally every 2.5ms, i.e., at a 400Hz rate (times are based on internal oscillator without external capacitor). The 6 bits read from the Data Memory are decoded in the ROM to the 17 (15 for ICM7243B) segment signals, which drive the SEGment outputs. Both CHARacter and SEGment outputs are disabled during WR operations (with SEN high and DISPlay FULL Low for Sequential Access mode). The outputs may also be disabled by pulling OSC/OFF low. The decode pattern from 6 bits to 17 (15) segments is done by a ROM pattern according to the ASCll font shown. Custom decode patterns can be arranged, within these limitations, by consultation with the factory.
By adding external capacitance toregardingat theCorporation and its products, see web site For information VDD Intersil OSC/OFF
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